Register examples

This page reproduces all diagrams from the register package documentation (v2.0, Matthew Lovell). Every example uses the .. register:: directive. Field descriptions are written with .. regdesc::.

Diagnostic Control (Register 2.1)

A 64-bit register with a large number of single-bit control and mask fields. This example demonstrates how the register package handles narrow fields by rotating the field names at 45°.

Function Class (Register 2.2)

A 64-bit PCI function class register with field descriptions. This example is taken from the register package documentation and shows the combination of a register diagram with a .. regdesc:: block.

BIST

(Read only) Always returns 0.

Header Type

(Read only) Always returns 0.

Latency Timer

PCI Latency Timer value (PCI 2.2 spec, Section 6.2.4).

Line Size

PCI Cache Line Size (PCI 2.2 spec, Section 6.2.4). Valid values are listed below; any other value will be treated as indicating 64 byte cache lines.

  • 0010 0000 — 128 bytes

  • 0001 0000 — 64 bytes

Class Code

(Read only) PCI Class Code (PCI 2.2 spec, Section 6.2.1). Chip identifies itself as a Host bridge.

Revision

(Read only) Chip revision number. Bits 4-7 provide the major revision number, and bits 0-3 provide the minor revision number.

Example register (Register 3.1)

The worked example from section 3 of the register documentation. A 64-bit register split across two rows using \regnewline.

Configuration (Register 3.2)

A 64-bit configuration register showing the regdesc / reglist field description pattern from the register documentation.

line_2x_enable

Setting this bit enables the chip to utilize a second connected data line.

SBA enable

Setting this bit activates the sideband-address port. The SBA port is only useable in a double-line configuration.

DVI disable

Setting this bit turns off DVI extraction for DMA requests.

LPCE

Line Parity Check Enable.

ill_cmd_enable

Illegal Command enable.

line_2x_L

(Read only) Indicates whether this chip is connected to a second data line. When this bit is 0, a second line is available.

Request Depth

Controls number of outstanding DMA requests.

Test mode

Activates data line test mode.

soft reset perf

Indicates that a soft reset has been performed.

Color Example (Register 3.3)

The same register as section 3.1, but with selected fields given background colours using the :color: option.

Address and BE phases (Figure 1)

Figure 1 from the register documentation — a register diagram produced without reset values using \regfieldb. This is an unnumbered figure rather than a register float in the original document; here it is rendered as a .. register:: directive.

Register with no offset

The register package allows the address argument to be empty. In that case the caption shows only the register name.

The register package allows the address argument to be empty. In that case the caption shows only the register name.

This is an example caption for Control Word.

Wide register with many rows

A 64-bit register split into two 32-bit rows, demonstrating \regnewline and the \regBitWidth / :bitwidth: option.

Valid

Set to 1 when this descriptor entry is valid and ready for processing.

Type

Descriptor type. 000 = data, 001 = command, 010 = status.

Length

Transfer length in bytes minus one. Maximum transfer is 4096 bytes.

Flags

Control flags. Bit 7: interrupt on completion. Bit 6: chain to next descriptor. Bits 5-0: reserved, must be zero.

Priority

Arbitration priority. Higher values indicate higher priority.

Base Address

32-bit physical address of the associated data buffer.

List of registers

Finally, .. listofregisters:: generates the complete list of registers.

Warning

Be aware that register’s \listofregisters command has been redefined in this project.

listofregisters was meant to be used as an Index (a table of figures of sort), not as a simple list of registers in the document. This rendering does not fit well for HTML outputs, where an index may cause headaches with over-filled indexes, reference collisions, and indexed captions.

Instead of having two wildly different outputs, Archware’s design decision has been to uniform the output as a bullet list with links to each register (referenced by name and address).